The trend to continue to miniaturize semiconductor integrated circuits to achieve submicron feature sizes and increase the number of devices fabricated on the integrated circuit has required smaller isolation areas between devices. In addition, step coverage has posed a major problem for integrated circuit manufacturers even into the late 1980s. Poor step coverage can be found at the sharp vertical step metal to substrate contacts, metal to metal vias, and metal crossovers. As dimensions shrink, conventional techniques used to improve step coverage fall short of expectations and are limited to stringent design criteria.
Forming reliable submicron contacts for integrated circuit applications has received widespread attention in the microelectronics industry. Metal films, for example, are used extensively for surface wiring. The metallization process of wiring components together begins with etching contact openings or vias through the various layers down to the active regions within a semiconductor substrate, or to contact an underlying polycrystalline silicon or a metal interconnect layer. A conductive metal is then deposited over the surface of the wafer in a manner that provides good contact with the underlying active devices. Increasing chip density and smaller geometries have decreased the available area for surface wiring.
Because of its physical properties, aluminum is especially well suited for fabrication of metal interconnects. Among the properties which make aluminum so useful is the fact that it is very conductive, it forms a good mechanical bond with various dielectric layers generally used in the semiconductor industry, and it makes a good ohmic contact with both N and P type semiconductors. However, the sputtering process used to apply aluminum thin film layers to an integrated circuit generally results in less than ideal filling of contact vias. Large aluminum grains tend to form on the upper surface of the insulating layer. These grains which form at the edges of the contact via tend to block the contact opening before the aluminum has a chance to completely fill the contact via. This blockage produces a thinner layer of aluminum along the sides of the insulating layer, resulting in voids and uneven structures within the via. This blockage also leads to non-uniform current densities in the metal interconnect. This problem is enhanced as circuit devices are fabricated using smaller geometries.
The uneven thickness of the aluminum layer going into the via, caused by the step coverage problem described above, has an adverse impact on device functionality. If the voids in the via are large enough, contact resistance can be significantly higher than desired. In addition, the thinner regions of the aluminum layer will be subject to the well known electromigration problem. This problem can cause eventual open circuits at the contacts and premature failure of the devices. The devices must be designed so that the current density in the aluminum interconnect lines does not become high enough to cause rapid electromigration. The thinner regions of the aluminum layer tend to occur over abrupt height changes on the surface of the integrated circuit. Many approaches have been used to try to ensure good metal contact to lower interconnect levels. For example, refractory metal layers have been used in conjunction with the aluminum interconnect layer to improve conduction through a via. Sloped via sidewalls have been used to improve metal filling in the via. The use of sloped sidewalls is becoming less common, however, as device sizes shrink because they consume too much area on a chip.
Even with these techniques, the problems of completely filling a via with aluminum are not solved. In part, this is due to the fact that aluminum is deposited at a temperature which tends to encourage fairly large grain sizes. Voids and other irregularities within the contact continue to be problems with current technologies.
It is therefore an object of this invention to provide a technique for manufacturing reliable submicron contacts for integrated circuits which meet smaller device geometry design requirements.
It is a further object of this invention to provide a method whereby contact openings are partially filled while capacitance remains low.
It would further be desirable to provide such a technique for increasing the planarity of the integrated circuit for deposited aluminum.
It is further desirable that such a technique be compatible with current standard process flows.